Integrated circuit (IC) design may be facilitated with an electronic design automation (EDA) tool that receives a behavioral description of a circuit and outputs a structural description of the circuit. A designer may use the EDA tool to interactively position and connect various components on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design. The structural description of the IC defines the fabrication of the IC. The designed IC is fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the IC.
After or during the design and creation of an IC layout, validation, optimization, and verification operations are performed on the IC layout using a set of testing, simulation, analysis and validation tools. These operations are conventionally performed in part to detect and correct placement, connectivity, and timing errors. For example, as part of the verification, the IC layout may undergo circuit simulation and analysis, which include testing signals between components. ICs have traditionally been characterized by the clock frequency at which they operate. Measuring the ability of a circuit to operate at a specified speed requires an ability to measure, during the design and verification processes, the delay of the circuit at various steps. One way to measure the delay is using static timing analysis (STA).
STA is a method of computing an expected timing of a digital circuit without requiring a lengthy and cost-prohibitive full simulation of the circuit. STA may be a feature of an EDA tool. STA may be used to determine whether clocks and signals are correctly timed. During STA, models of the expected timing of a digital circuit are created by estimating the expected delay within the circuit, for example, via an anticipated worst case signal path. The estimation of the expected delay may be based on graph-based analysis (GBA) or path-based analysis (PBA). GBA is more pessimistic than PBA because GBA takes a worst-case approach for slew propagation, wave forms, and derating. By contrast, PBA only propagates actual slews on the path and generally yields more accurate slew estimations.
An STA operator may be interested in the accuracy of the timing analysis between releases of a product designed and/or tested with a particular EDA timing tool. Users may also be interested in whether a timing violation may be ignored (i.e., whether a design may be signed off despite an outstanding violation), particularly at later stages of timing sign-off. These questions may be answered based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulation, which is typically more accurate than STA. Indeed, conventional methods involve manual comparison, by a user, of a SPICE-generated result and an STA-generated result. However, this requires user expertise in both SPICE- and STA-style timing reports. Thus, there is a need in the art to facilitate examination of SPICE-based simulation results in an STA context.